Browsing by Author "Altindal S."

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21.2 mV/K High-Performance Ni(50 nm)-Au(100 nm)/Ga2O3/p-Si Vertical MOS Type Diode and the Temperature Sensing Characteristics with a Novel Drive Mode
(2022-12-15) Cicek O.; Arslan E.; Altindal S.; Badali Y.; Ozbay E.
Sensitivity (S) and drive mode are crucial issues for the vertical metal-oxide-semiconductor (MOS) type diode applied in temperature sensing. In this study, experimentally, we indicated that the {S} values of the Ni50nm - Au100nm /Ga2O3/ p -Si vertical MOS type diode, using the measured capacitance-voltage (Cm - V) outputs, are obtained with a novel drive mode. We applied the constant capacitance mode to drive the silicon thermo-diodes as well as constant current mode, and constant voltage mode, which are known as two different methods in the literature. Meanwhile, the S value is 21.2 mV/K at 1 nF. This value is the highest value proven in the literature excepting the cryogenic temperature region, and near room temperature. This study provided an original structure for the silicon thermo-diodes and a novel way to drive them.
A Highly Sensitive Temperature Sensor Based on Au/Graphene-PVP/n-Si Type Schottky Diodes and the Possible Conduction Mechanisms in the Wide Range Temperatures
(2020-12-01) Cicek O.; Altindal S.; Azizian-Kalandaragh Y.
We report that the sensitive temperature response and possible Conduction Mechanisms (CMs) of Au/graphene-PVP/ ${n}$ -Si type Schottky diodes (SDs) are investigated using the standard Thermionic Emission (TE) theory at low temperatures (LTs) and high temperatures (HTs). The obtained results indicate that the zero-apparent barrier height ( $\phi _{\textit {Bo}}$ - $\phi _{\textit {ap}}$ ) increases while the ideality factor ( ${n}$ ), series and shunt resistances ( ${R} _{s}$ , ${R} _{\textit {sh}}$ ), rectifying rate (at ±2V) and surface states ( ${N} _{\textit {ss}}$ ) decrease with increasing temperature. The $\phi _{\textit {Bo}}$ , ${n}$ and ${R} _{s}$ values are also extracted from Cheung's functions and, then compared with those obtained TE theory. The conventional Richardson plot ( $\ell {n}$ ( ${I} _{o}$ /T 2)-q/kT) displays the deviation from the linearity at low-temperatures ( $T\le140$ K). Besides, the experimental value of Richardson constant ( ${A} ^{\ast }$ ) deduced from the intercept of plot was found to be several orders lower than the theoretical value. The discrepancies and higher values for the parameter of ${n}$ are important evidences for the deviation from TE theory. This is mainly attributed to the spatial inhomogeneities of the barrier height and potential fluctuations at the interface including low/high barrier areas. Hence the CMs across diode preferentially flows through these lower barriers/patches at the regions of LTs. The decrement in the ${N} _{\textit {ss}}$ with the enhancement in the temperature is in relation to the molecular restructuring-reordering under temperature and voltage effects. The SDs fabricated with graphene-PVP interlayer exhibit a higher sensitivity ( ${S}$ ) rather than many silicon/SOI-based structures. Numerically, the ${S}$ values are found to be in a range of 1.3 mV/K (LTs)/-1.93mV/K (HTs) in case of ${I} =0.1\,\,\mu \text{A}$ as against much greater values of -8.2 mV/K (LTs)/-7.9mV/K (HTs) for ${I} = 10\,\,\mu \text{A}$.
High Dielectric Performance of Heterojunction Structures Based on Spin-Coated Graphene-PVP Thin Film on Silicon with Gold Contacts for Organic Electronics
(2022-01-01) Cicek O.; Koca G.; Altindal S.
The letter reports that frequency response of heterojunction structure based on a spin-coated graphene-PVP thin film on silicon with gold Schottky contacts and the electronic properties obtained by using capacitance (C) and conductance (Gω) versus voltage characteristics in the frequency range from 5 to 5 MHz. Furthermore, the electronic magnitudes were calculated. The accumulation capacitance observed at 3 V changes from 920 to 1094 pF. Here, empirically, the C and G/ω values increased with a decreasing frequency, while increasing in depletion and accumulation regions with increasing voltages. However, particularly, the Rs - V - f curves have peaks in low frequency values in the accumulation and depletion regions, these peaks decreased at high frequencies. Besides, an interface trap state density of 5.6- 6.58×10 12 cm-2.eV-1 with a relaxation time constant of 157- 31.5 μ s was deduced. Additionally, the frequency and dc bias voltage-dependent dielectric characteristics show a huge dispersion, at room temperature. Experimentally, the high dielectric constant (max) is 111 which is very higher than the maximum value of the conventional materials (SiO2 (3.8), SnO2 (7.5), and so on) and appropriate doped materials to PVP. The results indicate that the graphene-PVP thin film with the high max value has a potential in metal-organic-semiconductors device technologies instead of a conventional device.
MBE-growth and characterization of InxGa1-xAs/GaAs (x=0.15) superlattice
(2008-01-01) Sarikavak B.; Öztürk M.K.; Altuntaş H.; Mammedov T.S.; Altindal S.; Özçelik S.
A qualified In0:15Ga0:85As/GaAs superlattice was grown on an n-type GaAs(100) substrate by molecular beam epitaxy(MBE). Analysis of this structure was first carried out by X-Ray diffraction(XRD) and this structure's the interface thicknesses, roughness and x concentration determined at nanoscale. Secondly, the electrical characteristics of this sample such as the current-voltage-temperature (I-V-T), capacitance-voltage-temperature (C-V-T) and conductance-voltage temperature (G-V-T) were studied over a wide temperature range. The energy distribution of interface states was determined from the forward bias I-V characteristics by taking into account the bias dependence of the effective barrier height. Experimental results show that the forward and reverse I-V characteristics are similar to Schottky-junction behavior. The ideality factor n, series resistance Rs, barrier height φ{symbol} B and density of interface states Nss were found to be strong functions of temperature. According to thermionic emission (TE) theory, the zero-bias barrier height (φ{symbol}Bo) calculated from forward bias I-V characteristics was found to increases with increasing temperature. In addition, the value of Rs as a function of both voltage and temperature was obtained from C-V and G-V characteristics. The temperature dependent of I-V, C-V and G-V characteristics confirmed that the distribution the Rs and Nss are important parameters that influence the electrical characteristics of these devices.
Vertical CdTe:PVP/p-Si-Based Temperature Sensor by Using Aluminum Anode Schottky Contact
(2022-12-01) Cetinkaya H.G.; Cicek O.; Altindal S.; Badali Y.; Demirezen S.
The vertical Schottky barrier diode (SBD)-based temperature sensors with the drive modes are a significant issue with more advantageous than the on-chip sensor. The sensitivity (S) and the current conduction mechanisms (CCMs) of the vertical cadmium telluride (CdTe):polyvinyl pyrolidone (PVP)/ p-Si SBD were studied experimentally over the range of 80-340 K and compared with that of the lateral and vertical sensors. It is shown that the low and moderated voltages of the CdTe:PVP/ p-Si corresponding two linear regions of the current-voltage (I-V) outputs are around 0.1-0.3 and 0.4-0.65 V, respectively. The variation of Schottky barrier height (BH; ΦBo) and ideality factor (n) with temperature was obtained according to two linear regions. Energy dispersion of the interface traps (Nss) with changing temperature is additionally analyzed quantitatively. It is concluded that the thermionic-emission (TE) theory with double-Gaussian distribution (GD) is the dominant mechanism resulting the I-V characteristics of the vertical CdTe:PVP/ p-Si SBD in this study. Moreover, in the constant current, the S values at the drive current of 10, 20, and 50μA were resulting in a range of -1.6 to -1.8 mV/K.